• IC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idr
  • IC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idr
  • IC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idr
  • IC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idr
  • IC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idr
  • IC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idr

IC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idr

shape: Surface Mount
Conductive Type: Unipolar Integrated Circuit
Integration: GSI
Technics: Semiconductor IC
Application: Specific Integrated Circuits
Type: Digital / Analog IC
Samples:
US$ 10/Piece 1 Piece(Min.Order)
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Basic Info.

Model NO.
TLC555IDR
Transport Package
Carton
Specification
10*10*10cm
Trademark
FT
Origin
China
HS Code
85416000
Production Capacity
100000

Product Description

Description

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device supports smaller timing capacitors than those supported by the NE555 or LM555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flipflop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.
IC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idrIC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idrIC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idrIC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idrIC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idr


IC Osc Sgl Timer 2.1MHz 8-Soic 555 Type, Timer/Oscillator (Single) IC Tlc555idr

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