• Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)
  • Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)
  • Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)
  • Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)
  • Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)
  • Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)

Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)

shape: Surface Mount
Conductive Type: Unipolar Integrated Circuit
Integration: GSI
Technics: Semiconductor IC
Manufacturer: Avtoriginal
Type Application: DVD Player
Samples:
US$ 10/Piece 1 Piece(Min.Order)
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Overview

Basic Info.

Model NO.
CY2305SXC-1H
Transport Package
Carton
Specification
10*10*10cm
Trademark
FT
Origin
China
HS Code
85416000
Production Capacity
100000

Product Description

Product Description

The CY2309 is a low-cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100-/133 MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

The CY2309 has two banks of four outputs each, which can be controlled by the select inputs as shown in Select Input Decoding on page 5. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes.
The CY2305 and CY2309 PLLs enter a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25.0 μA current draw for these parts. The CY2309 PLL shuts down in one additional case as shown in Select Input Decoding on page 5.
Multiple CY2305 and CY2309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps.
The CY2305/CY2309 is available in two or three different configurations, as shown in Ordering Information on page 16. The CY2305-1/CY2309-1 is the base part. The CY2305-1H/ CY2309-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1.
Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)

Fanout Buffer (Distribution) , Zero Delay Buffer IC 133.33MHz 1 8-Soic (0.154", 3.90mm Width)

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