• Clock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, Csp
  • Clock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, Csp
  • Clock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, Csp
  • Clock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, Csp
  • Clock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, Csp
  • Clock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, Csp

Clock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, Csp

shape: Surface Mount
Conductive Type: Unipolar Integrated Circuit
Integration: GSI
Technics: Semiconductor IC
Application: Specific Integrated Circuits
Type: Digital / Analog IC
Samples:
US$ 10/Piece 1 Piece(Min.Order)
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  • Product Description
Overview

Basic Info.

Model NO.
AD9510BCPZ
Manufacturer
Analog Devices Inc.
Voltage - Power Supply
3.135V ~ 3.465V
Package/Housing
64-Vfqfn Exposed Pad, Csp
Transport Package
Carton
Specification
10*10*10cm
Trademark
FT
Origin
China
HS Code
85416000
Production Capacity
100000

Product Description

Product Description

The AD9510 provides a multi-output clock distribution function along with an on-chip phase-locked loop (PLL) core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this device. The PLL section consists of a programmable reference divider (R); a low noise, phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external voltage-controlled crystal oscillator (VCXO) or voltage-controlled oscillator (VCO) to the CLK2 and CLK2B pins, frequencies of up to 1.6 GHz can be synchronized to the input reference. There are eight independent clock outputs. Four outputs are low voltage positive emitter-coupled logic (LVPECL) at 1.2 GHz, and four are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels.

 
Clock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, CspClock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, CspClock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, CspClock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, CspClock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, Csp


Clock Fanout Buffer (Distribution) , Divider IC 2: 8 1.2 GHz 64-Vfqfn Exposed Pad, Csp

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